Various issues arise in attempting to satisfy the ever increasing demands for miniaturization, particularly in fabricating non-volatile semiconductor devices, such as flash memory devices, e.g., electrically erasable programmable read only memory (EEPROM) devices. The demands for continuing miniaturization have led to the fabrication of flash memory devices comprising transistors having a gate width of about 0.13 micron and under and gate structures spaced apart by a small gap of about 0.30 micron or less. In accordance with conventional practices, an oxide sidewall spacer is formed on side surfaces of the gate stack, thereby reducing the gap to about 0.125 micron, and a conformal silicon nitride layer deposited thereon. The first interlayer dielectric (ILDO) is then deposited over the gate structures filling the gaps therebetween. Rapid thermal annealing is then conducted, as at a temperature of about 820° C. for about 120 seconds.
As miniaturization proceeds apace, various reliability issues arise, particularly as EEPROM device dimensions are scaled into the deep sub-micron regime, such as data retention losses and the difficulty in filling the gaps without void formation. Charge losses (data retention) cause undesirable delays in production from increased manufacturing costs.
Accordingly, there exists a need for semiconductor devices, such as flash memory devices, e.g., EEPROMS, with improved reliability and increased operating speed, and for efficient enabling methodology. There exists a particular need for methodology enabling the fabrication of flash memory devices, such as EEPROM devices, with improved data retention and improved reliability.